1. Field of the Invention
The present invention relates to a method and related apparatus for data error checking, and more particularly, to a method and related apparatus for performing data error checking/correction while accessing a higher data-rate memory.
2. Description of the Prior Art
In the current information society, computer systems are widely used in many aspects of life. Besides some general applications of personal computers or servers, such as an automatic teller machine, some vending machines and information appliances also have embedded computer systems. For different applications, different computers may have different system requirements. For example, a personal computer/server usually requires higher efficiency and scalability, but a financial service terminal, such as an automatic teller machine, has more need of data correctness. Therefore, how to meet requirements of every kind of computer system is a key research topic of information technology companies.
As known by those skilled in the art, a computer system usually comprises a central processing unit, memory, chipset, and other peripheral devices, such as a hard drive, CD-ROM, input/output interface, and network-accessing device. The central processing unit controls the operation of the computer system to execute programs and process data. The memory, such as a random access memory, stores programs and data needed by the central processing unit during operation. The chipset, which is coupled between the central processing unit and the memory, manages data access between the central processing unit (or other devices) and the memory. In addition, the chipset also can perform data error checking/correction to ensure data correctness.
In a mainstream memory architecture, such as the memory architecture of a personal computer, the chipset can access data in the memory via a 64-line bus, that is, the chipset can access 64-bit data via the bus. In order to ensure correctness of 64-bit data, a “64-bit data/8-bit error checking code” algorithm has been developed to generate an 8-bit error checking code according to a 64-bit data for performing data error checking/correction. In other words, under such mechanism, apart from the 64-line bus for accessing data, there must be an extra 8-line bus for transmitting 8-bit error check codes.
In the prior art, the operation of data error checking/correction performed by the chipset can be described as follows. When the chipset intends to store 64 bits of data into the memory, the chip first uses the “64-bit data/8-bit error checking code” algorithm to generate an 8-bit error checking code according to the 64-bit data, and then stores the 64-bit data with the 8-bit error checking code into the memory. When the chipset accesses the 64-bit data from the memory, the 8-bit error checking code will be accessed by the chipset in the meantime for reference. After accessing the 64-bit data, the chipset uses the “64-bit data/8-bit error checking code” algorithm again to generate another new 8-bit error checking code according to the accessed 64-bit data, and then compares the new 8-bit error checking code with the original 8-bit error checking code to check whether these two 8-bit error checking codes match each other. If so, this means the accessed 64-bit data is correct; if not, then the accessed 64-bit data must be damaged and have some error. Under such situation, according to the error checking code, the chipset can perform a corresponding error management process to judge the type and location of the error, or even to repair the accessed 64-bit data or report the error to the central processing unit in order to inform the computer system user.
In the applications of the personal computer/server, the memory is composed of memory modules, and the current mainstream memory module comprises nine memory units (memory chips). Each memory unit can provide an 8 bits of data, therefore a memory module totally can provide 72 bits for data transmission at one time. That is, the memory module is able to support the “64-bit data/8-bit error checking code” algorithm, when accessing 64 bits of data from eight memory units using the 8-bit error checking code for performing data error checking/correction.
Although the above error checking/correction mechanism has already become a standard in the information industry, it still lacks flexibility. It is difficult to apply in some low-cost computer systems, which have simpler embedded architecture. For implementing the “64-bit data/8-bit error checking code” algorithm, the prior art accesses 64 bits of data from the memory to generate a corresponding 8-bit error checking code. However, in financial service terminals, it will cost too much to use nine memory units to build a memory. However, when using fewer memory units to build a memory, the prior art cannot access 64 bits of data at a time and so the “64-bit data/8-bit error checking code” algorithm cannot be implemented for performing data error checking/correction. For example, a low-cost computer system usually uses four memory units to build a memory in order to provide 32-bit data, but under such situation, the prior art can only accesses 32 bits of data at a time, which is not conducive to implementation of the “64-bit data/8-bit error checking code” algorithm. Moreover, this increases the complexity and cost if designing a new algorithm for a 32-bit data structure. Moreover, as known by those skilled in the art, 32-bit data requires a 6-bit error checking code to perform data error checking/correction; thus compared with the “64-bit data/8-bit error checking code” algorithm, the “64-bit data/8-bit error checking code” algorithm is more economic. Because in the “32-bit data/6-bit error checking code” algorithm, each bit of data needs 0.1875 bits of error checking code; yet in the “64-bit data/8-bit error checking code” algorithm, each bit of data only needs 0.1275 bits of error checking code.